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8.4 I/O Primary and Secondary Address Configurations
When the system decodes the Primary and Secondary Address Configurations, the registers are accessed in the
block of I/O space as shown in Table 46 .
As for the Memory Mapped Addressing, register 0 is accessed with – CE1 Low and –CE2 Low (and A0 don’t Care) as a
Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with – CE1
Low and – CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the
address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –
CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with
– CE1 High and – CE2 Low accesses the error (read) or feature (write) register.
Table 46: Primary and Secondary I/O Decoding
- REG
0
0
0
0
0
0
0
0
0
0
A9 to A4
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
1F(17)h
3F(37)h
3F(37)h
A3
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
1
1
1
1
1
1
A1
0
0
1
1
0
0
1
1
1
1
A0
0
1
0
1
0
1
0
1
0
1
- IORD=0
Even Data Register
Error Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Status Register
Alternate Status Register
Drive Address Register
- IOWR=0
Even Data Register
Feature Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Command Register
Device Control Register
Reserved
8.5 True IDE Mode Addressing
When the Card is configured in the True IDE Mode, the I/O decoding is as shown in Table 47 .
Table 47: True IDE Mode I/O Decoding
- CS1
1
1
1
1
1
1
1
1
1
0
- CS0
0
1
0
0
0
0
0
0
0
1
A2
0
X
0
0
0
1
1
1
1
1
A1
0
X
0
1
1
0
0
1
1
1
A0
0
X
1
0
1
0
1
0
1
0
-DMACK
1
0
1
1
1
1
1
1
1
1
- IORD=0
PIO RD Data
DMA RD Data
Error Register
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Alt Status
- IOWR=0
PIO WR Data
DMA WR Data
Features
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Command
Control Register
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 53 of 99
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